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Preliminary
RF2668
CDMA/FM TRANSMIT MODULATOR, IF AGC, AND UPCONVERTER WITH INTEGRATED PLL
5
Typical Applications
* CDMA/FM Cellular and PCS Systems * Tri-Mode/Dual-Band CDMA Applications * W-CDMA Systems
* Wireless Local Loop Systems * Spread-Spectrum Cordless Phones * High Speed Data Modems
Product Description
The RF2668 is an integrated complete quadrature modulator, IF AGC amplifier, upconverter, and PLL, designed for the transmit section of dual-mode CDMA/FM cellular, PCS, and tri-mode CDMA applications. It is designed to modulate baseband I and Q signals, amplify the resulting IF signals while providing 95dB of gain control range, and perform the final upconversion to UHF. Noise Figure, IP3, and other specifications are designed to be compatible with the IS-98 Interim Standard. This circuit is designed as part of RFMD's newest CDMA chipset, which also includes the RF2667 CDMA/FM Receive IF AGC and Demodulator. The IC is manufactured on an advanced 18GHz FT Silicon Bipolar process, and is supplied in a 48-lead plastic LQFP package. Optimum Technology Matching(R) Applied
9.00 + 0.20 sq. 0.35 0.25 0.50 7.00 + 0.10 sq.
5
MODULATORS AND UPCONVERTERS
0.22 + 0.05 7 MAX 0 MIN
1.40 + 0.05
0.60 + 0.15 0.10
0.127
Package Style: LQFP-48_7x7
uSi Bi-CMOS
MODE VCC3 BG 48 NC 1 NC 2 47 46 Band Gap Rel
Si BJT
GaAs HBT SiGe HBT
VCO_EN PLLISET MIX_EN PLLON TX_EN
GaAs MESFET Si CMOS
VREFPLL OSCREF
Features
* Supports Tri-Mode Operation * Digitally Controlled Power Down Modes
45
44
43
42
41
40
39
38
37 36 SET2 35 PLLVCC
Bias Supply /R Lock Detect Charge Pump
SET1
CE
* 2.7V to 3.3V Operation * Digital First LO Quadrature Divider * Double-Balanced UHF Upconvert Mixer * IF AGC Amp with 95dB Gain Control
RFOUT 3 VCC4 4 /N LO2+ 5 LO2- 6 GND2 7 GND2 8 MIX_DEC 9 MIX IN+ 10 MIX IN- 11 NC 12 13 NC 14 MOD OUT15 MOD OUT+ 16 GND1 17 AGC_DEC 18 VGC 19 VCC2 20 GND1 21 QSIG 22 QREF
34 PLLGND 33 LD 32 DO 31 VCO+ 30 VCO29 LO1+ 28 LO1-
Quad /2
27 VCC1 26 VCO_ISET 25 NC
Ordering Information
CDMA/FM Transmit Modulator, IF AGC, and Upconverter with Integrated PLL RF2668 PCBA-PCS/CEL Fully Assembled Evaluation Boards RF2668 PCBA-DO Fully Assembled Evaluation Boards RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com RF2668
23 IREF
24 ISIG
Functional Block Diagram
Rev B4 010423
5-71
RF2668
Absolute Maximum Ratings Parameter
Supply Voltage Power Down Voltage (VPD) I and Q Levels, per pin LO1 Level, balanced Operating Ambient Temperature Storage Temperature
Preliminary
Rating
-0.5 to +5 -0.5 to VCC + 0.7 1 +6 -40 to +85 -40 to +150
Unit
VDC V VPP dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Specification Min. Typ. Max.
Unit
Condition
T=25 C, VCC =3.0V, ZLOAD =200, LO1=-10dBm @ 260MHz, IF=130MHz, I SIG=Q SIG=300mVPP, RF Output externally matched Balanced Balanced Per Pin
5
MODULATORS AND UPCONVERTERS
I/Q Modulator & AGC
I/Q Input Frequency Range I/Q Input Impedance I/Q Input Reference Level LO1/FM Frequency Range LO1/FM Input Level LO1/FM Input Impedance Sideband Suppression Carrier Suppression Max Output, FM Mode Max Output, CDMA Mode 0 to 20 80 1.3 0 -15 35 40 +2.5 -3 -2 Min Output, CDMA Mode Output Power Accuracy Adjacent Channel Power Rejection @ 885kHz Adjacent Channel Power Rejection @ 1.98MHz Output Noise Power Output Impedance Current Consumption -3 -2 -60 -69 -117 200 40 -111 -10 200 40 27 50 30 +5 0 0 -95 800 -5 MHz k VDC MHz dBm dBc dBc dBc dBc dBm dBm dBm dBm dB dB dBc dBc dBm/Hz mA
-89 +3 +2
Balanced I/Q Amplitude adjusted to within 20mV Unadjusted I/Q DC Offset adjusted to within 20mV Unadjusted VGC =2.4VDC, T=-20C to +85C VGC =2.4VDC, T=-20C to +85C, IS-95A CDMA Modulation ISIG=QSIQ=300mVpp@ 100kHz VGC =0.3VDC, T=-20C to +85C, IS-95A CDMA Modulation T=-20 to +85 C, Ref=25 C 1.4VGC 2.5 IS-95A CDMA Modulation POUT = -5dBm IS-95A CDMA Modulation POUT = -5dBm POUT = -1dBm, T=-20C to +85C Balanced I/Q modulator and AGC only.
5-72
Rev B4 010423
Preliminary
Parameter
UHF Upconverter
General IF Input Impedance IF Input Frequency Range LO2 Input Impedance LO2 Input Level LO2 Input Frequency Range RF to LO2 Isolation LO Input VSWR Current Consumption Cellular Conversion Gain Noise Figure (SSB) Output IP3 200 0 -6 50 -3 30 <2:1 24 -1.5 -0.5 15 +13 400 0 2.5 MHz dBm GHz dB mA dB dB dBm
RF2668
Specification Min. Typ. Max. Unit Condition
Output externally matched Balanced Single Ended
50 UHF upconverter only. RFOUT =830MHz RFOUT =830MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =830MHz, LO2=960MHz@ -3dBm RFOUT = 830MHz RFOUT =1950MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =1950MHz, LO2=1570MHz @-3dBm RFOUT =1950MHz. See note on eval board schematic.
5
MODULATORS AND UPCONVERTERS
RF Output VSWR W-CDMA Conversion Gain Noise Figure Output IP3
<2:1 -1.5 TBD 10 dB dB dBm
RF Output VSWR Dual Output Cellular Conversion Gain Noise Figure Output IP3
<2:1
-1.5
-0.5 15 12.5
dB dB dBm
RF Output VSWR PCS Conversion Gain Noise Figure Output IP3
<1.5:1 -1.5 -1.0 15 10.5 dB dB dBm
RFOUT =830MHz RFOUT =830MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =830MHz, LO2=960MHz@-3dBm RFOUT =830MHz RFOUT =1880MHz RFOUT =1880MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =1880MHz, LO2=1750MHz @-3dBm RFOUT =1880MHz PLL locked with Loop BW =5kHz, Tank Values: 39nH and SMV1234 varactor.
RF Output VSWR
<1.5:2
VCO
Phase Noise @ 100kHz Current Consumption -110 1 100 0.8 4/Loop BW 4 dBc/Hz mA A VPP s mA
PLL
Charge Pump Current TCXO Input Level PLL Lock Time Current Consumption
PLL only.
Rev B4 010423
5-73
RF2668
Parameter
Power Supply
Supply Voltage Current Consumption Power Down Current VPD HIGH Voltage VPD LOW Voltage 2.7 3.0 69 <10 3.3 V mA A V V
Preliminary
Specification Min. Typ. Max. Unit Condition
Total device current.
VCC-0.3 0.3 Japan 333.7 19.2 192 100 32/33 9 104 3337 VCC GND Japan 333.7 19.8 198 100 32/33 9 104 3337 GND VCC US/Korea 260.76 19.68 252 78.09524 32/33 11 104 3339 GND GND
PLL Settings
Application LO Frequency, MHz Crystal, MHz Reference Divider Phase Detector Frequency, kHz Prescaler Swallow Counter (A) Fixed Divider (N) Net N in VCO Path SET1 SET2 IF Frequency =LO Frequency/2
5
MODULATORS AND UPCONVERTERS
5-74
Rev B4 010423
Preliminary
Pin 1 2 3 Function NC NC RF OUT Description
Not connected. Not connected. RF output pin. An external shunt inductor to VCC plus a series blocking/ matching capacitor are required for 50 output.
RF2668
Interface Schematic
VCC4
300 RF OUT
4
VCC4
5
LO2+
LO2+
LO2-
6 7 8 9 10 11
LO2GND2 GND2 MIX_DEC MIX IN+ MIX IN-
One half of the balance mixer LO2 input. In single ended applications, this pin is AC grounded with a 100pF capacitor. Ground connection for the mixer stage. For best performance, keep traces physically short and connect immediately to ground plane. Same as pin 7. Current Mirror decoupling pin. A 1000pF external capacitor is required to bypass this pin. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 11, except complementary input. One half of the 200 balanced impedance input to the mixer stage. This pin is NOT internally DC-blocked. An external blocking capacitor (1000pF recommended) must be provided if the pin is connected to a device with DC present. If no IF filter is needed this pin may be connected to MOD OUT+ through a DC blocking capacitor. An appropriate matching network may be needed if an IF filter is used. Not connected. Not connected. One half of the balanced AGC output port. The impedance of this port is 200 balanced. If no filtering is required, this pin can be connected to the MIX IN- pin through a DC blocking capacitor. This pin requires an inductor to VCC to achieve full dynamic range. In order to maximize gain, this inductor should be a high-Q type and should be parallel resonated out with a capacitor (see application schematic). This pin is NOT DC-blocked. A blocking capacitor of 2200pF is needed when this pin is connected to a DC path. An appropriate matching network may be needed if an IF filter is used. Same as pin 14, except complementary output. Ground connection for all baseband circuits including bandgap, AGC, flip-flop, modulator and FM amp. For best performance, keep traces physically short and connect immediately to ground plane.
See pin 5.
See pin 11.
BIAS BIAS
100
100
MIX IN-
MIX IN+
12 13 14
NC NC MOD OUT-
VCC3
VCC3
100
100 MOD OUTMOD OUT+
15 16
MOD OUT+ GND1
See pin 14.
Rev B4 010423
5-75
MODULATORS AND UPCONVERTERS
Supply for the mixer stage only. The supply for the mixer is separated to maximize IF to RF isolations and reduce the carrier leakage. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. One half of the balanced mixer LO2 input. In single-ended applications, the other half of the input, LO2- is AC grounded. This is a 50 impedance port. This pin is NOT internally DC-blocked. An external blocking capacitor (100pF recommended) must be provided if the pin is connected to a device with DC present.
BIAS
BIAS
5
50
50
RF2668
Pin 17 Function AGC_DEC Description
AGC decoupling pin. An external bypass capacitor of 1nF capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Analog gain control for AGC amplifiers. Valid control voltage ranges are from 0.3VDC to 2.4VDC. The gain range for the AGC is 95dB. These voltages are valid ONLY for a 39k source impedance. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins.
Preliminary
Interface Schematic
18
VGC
BIAS
21 k GC 40 k
19
VCC2
5
MODULATORS AND UPCONVERTERS
20 21
GND1 Q SIG
Supply for the modulator stage only. A 10nF external bypass capacitor is required and an additional 0.1F will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 16. Baseband input to the Q mixer. This pin is DC-coupled. The DC level of 1.3V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50k minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Reference voltage for the Q mixer. This voltage should be the same as the DC voltage supplied to the Q SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the Q SIG DC voltage may be adjusted. Input impedance of this pin is 50k minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins.
Q SIG Q REF
22
Q REF
See pin 21.
23
I REF
See pin 24. Reference voltage for the I mixer. This voltage should be the same as the DC voltage supplied to the I SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the I SIG DC voltage may be adjusted. Input impedance of this pin is 50k minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Baseband input to the I mixer. This pin is DC coupled. The DC level of 1.3V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50k minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Not connected. An external resistor of 47k is used to set the VCO current for minimum phase noise. Supply Voltage for the LO1 flip-flop and limiting amp only. This supply is isolated to minimize the carrier leakage. A 1nF external bypass capacitor is required, and an additional 0.1F will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. External LO input to modulator. Controlled by VCO_EN signal. Logic See pin 29. low is internal VCO, while logic high is external VCO.
I SIG I REF
24
I SIG
25 26 27
NC VCO_ISET VCC1
28
LO1-
5-76
Rev B4 010423
Preliminary
Pin 29 Function LO1+ Description
External LO input to modulator. Controlled by VCO_EN signal. Logic low is internal VCO, while logic high is external VCO.
RF2668
Interface Schematic
1 k LO1+, FM+
30 31
VCOVCO+
See VCO+ description. This port is used to supply DC voltage to the VCO as well as to tune the center frequency of the VCO. Equal value inductors should be connected to this pin and pin 30 although a small imbalance can be used to tune in the proper frequency range. Output of the charge pump, and input to the VCO control. An RC network from this pin to ground is used to establish the PLL bandwidth. Lock detector output for synthesizer. Requires external transistor to provide hysteresis and inversion of signal. See Application circuit. Ground for synthesizer. For best performance, keep traces physically short and connect immediately to ground plane. Supply for the PLLVCC only. A 10nF external bypass capacitor is required and an additional 0.1F will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. PLL Setting (Divider) pin. See the PLL settings table. Same as pin 36. TCXO reference input for synthesizer. Bypass pin for the synthesizer reference voltage. Current setting pin for synthesizer charge pump. For normal operation, a 390 resistor to ground should be used to set the current. Synthesizer Enable pin. VCO Enable pin. Switches between internal and external VCO. Power down control for mixer only. When connected to logic "high" (>VCC -0.3) the mixer circuits are operating; when connected to ground (0.3V), the mixer is turned off but all other circuits are operating. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins.
32 33 34 35
DO LD PLLGND PLLVCC
5
MODULATORS AND UPCONVERTERS See pin 45. See pin 45.
1 k MIX EN 450
10 k CE
36 37 38 39 40 41 42 43
SET2 SET1 OSCREF VREFPLL PLLISET PLLON VCO_EN MIX_EN
44 45
TX_EN CE
Shuts down the entire TX path. VCO is still active when TX disabled. Logic high (>VCC -0.3) for TX Enable. Power down control for overall circuit. When logic "high" (VCC -0.3V), all circuits are operating; when logic "low" (0.3V), all circuits are turned off. The input impedance of this pin is >10k. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the VCC pins. Selects between CDMA and FM mode. This is a digitally controlled input. A logic "high" (VCC -0.3VDC) selects CDMA mode. A logic "low" (<0.3VDC) selects FM mode. In FM mode, this switch enables the FM amplifier and turns off the I&Q modulator. The impedance on this pin is 30k. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins.
46
MODE
BIAS
60 k MODE 60 k
Rev B4 010423
5-77
RF2668
Pin 47 Function VCC3 Description
Supply voltage for the AGC and the Bandgap circuitry. A 1nF external bypass capacitor is required and an additional 0.1F will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Bandgap voltage reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 1nF external bypass capacitor is required.
Preliminary
Interface Schematic
48
BG OUT
5
MODULATORS AND UPCONVERTERS
5-78
Rev B4 010423
Preliminary
Pin-Out
VREFPLL OSCREF VCO_EN PLLISET MIX_EN
RF2668
PLLON
TX_EN
MODE
VCC3
48 NC 1 NC 2 RFOUT 3 VCC4 4 LO2+ 5 LO2- 6 GND2 7 GND2 8 MIX_DEC 9 MIX IN+ 10 MIX IN- 11 NC 12 13 NC
47
46
45
44
43
42
41
40
39
38
37 36 SET2 35 PLLVCC 34 PLLGND 33 LD 32 DO 31 VCO+ 30 VCO29 LO1+ 28 LO127 VCC1 26 VCO_ISET 25 NC
SET1
BG
CE
5
MODULATORS AND UPCONVERTERS
14 MOD OUT-
15 MOD OUT+
16 GND1
17 AGC_DEC
18 VGC
19 VCC2
20 GND1
21 QSIG
22 QREF
23 IREF
24 ISIG
Rev B4 010423
5-79
RF2668
Application Schematic Single- or Dual-Mode Operation
VCC MODE CE AGC MIX EN VCO EN PLL ON 270
Preliminary
1 nF OSC REF 10 nF SET1
1 nF VCC
SET2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 /R Lock Detect Charge Pump 34 33 32 31 30 29 28 200 3.9 k LO1+ LO1VCC 26 25 13 14 15 16 VCC VCC 10 nF 1 nF 10 nF 10 nF 17 18 19 20 21 22 23 24 47 k 10 nF ** 39 nH ** VTUNE DO D1 39 nH 10 nF LD 1 nF 2.2 nF 10 nF
10 nF
1 2 3 4
Band Gap Rel
Bias Supply
12 nH 2 pF RF OUT VCC 10 nF
5
MODULATORS AND UPCONVERTERS
/N 5
36 k
220 pF
33 pF VCC DO
LO2 100 pF 6 7 8 1 nF 9 1 nF MIX IN+ MIX IN1 nF 12 10 11
100 pF
Quad /2
27
L1* MOD OUT-
L2* 1 nF 39 k
MOD OUT+ *L1 and L2 are the bias choke inductor. **Denotes components not normally populated. VGC OSIG REF ISIG
5-80
Rev B4 010423
Preliminary
Application Schematic Tri-Mode/Dual-Band Operation
VCC MODE CE AGC MIX EN VCO EN PLL ON 270 1 nF
RF2668
OSC REF 10 nF SET1 VCC 1 nF 12 nH 4.7 pF RF OUT (CELL) 2 8.2 nH RF OUT (PCS) 3.9 nH 10 nF 5 LO2 100 pF 6 7 8 1 nF 9 1 nF MIX IN+ MIX IN1 nF 12 13 14 15 16 VCC VCC 10 nF L1* MOD OUT1 nF 39 k MOD OUT+ *L1 and L2 are the bias choke inductor. **Denotes components not normally populated. VGC OSIG REF ISIG L2* 1 nF 10 nF 10 nF 17 18 19 20 21 22 23 24 25 47 k 10 11 28 31 30 29 200 3.9 k ** 39 nH ** VTUNE DO LO1+ LO10.5 pF VCC 3 4 /N /R Lock Detect Charge Pump 8 nH 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 D1 39 nH 10 nF LD 1 nF 2.2 nF 10 nF
10 nF
SET2
4.7 pF
1
Band Gap Rel
Bias Supply
36 k
220 pF
33 pF VCC DO
100 pF
5
MODULATORS AND UPCONVERTERS
Quad /2
27 26
10 nF
VCC
Rev B4 010423
5-81
RF2668
Evaluation Board Schematic RFOUT =830MHz
(Download Bill of Materials from www.rfmd.com.)
Preliminary
CE R6*
Q1 PNP Zetex FMMT3906TA
LD
R5 510 C25 10 nF
LD OUT R10 510 k
MIX EN P1 1 2 3 4 MODE CE TX EN MIX EN VCO EN VCC 6 7 PLLON SET1 SET2 GND LDOUT J1 RF OUT 50 strip C18 10 nF L1 12 nH C1 1 nF 1 2 48 47 46 45 44 43 AGC CE MODE VCC C2 10 nF
VCO EN PLL ON R3 270 C19 1 nF 50 strip J8 OSC REF SET1 C20 10 nF 36 35 /R Lock Detect Charge Pump 34 33 32 31 30 29 28 T3 T4-1 R7 200 R2 47 k C13 10 nF 50 strip C16** D1 LD C26 1 nF C21 2.2 nF R4 36 k L3 39 nH L2 39 nH C17 10 nF R8** C22 220 pF C27 33 pF DO VCC SET2
5
MODULATORS AND UPCONVERTERS
5
42
41
40
39
38
37
8 9 10 P2 1 2 3
Band Gap Rel
Bias Supply
C3 2 pF
3 C4 10 nF 50 strip C5 100 pF C6 100 pF 4 /N 5 6 7 8 9
VCC REF GND VGC J2 LO2
P3 1 2 3 VTUNE GND VCC J3 MIX IN 50 strip T1 T4-1
VTUNE R9 3.9 k DO J7 L01
C7 1 nF C8 1 nF
10 11
Quad /2
27 26 25
C9 1 nF
2668400A
12 13 T2 T4-1 C11 1 nF C10 10 nF R1 39 k VCC C23 10 nF 14 15 16 17 18 19 20 21 22 23 24
VCC
J4 MOD OUT
50 strip
50 strip
J6 ISIG REF
NOTE: To tune the board for RF OUT = 1950 MHz, change L1 to 2.2 nH. **Denotes not normally populated. VCC
C12 1 nF
C23 10 nF 50 strip
J5 OSIG
VGC
5-82
Rev B4 010423
Preliminary
Evaluation Board Schematic Dual Output Band
P1 1 2 3 4 5 6 7 8 9 10 P2 1 2 3 REF GND VGC C6 100 pF C7 1 nF VTUNE GND VCC J3 MIX IN 50 strip T1 T4-1 C8 1 nF MODE CE TX EN MIX EN VCO EN PLLON SET1 SET2 GND LDOUT J9 Cellular RF OUT J1 PCS RF OUT L8* 50 strip C29 3 pF C3 0.5 pF L1 100 nH L7 22 nH L5 10 nH C4 10 nF C18 10 nF C2 10 nF R3 270 C19 1 nF 50 strip VCC VCC MODE CE TX EN MIX EN VCO EN PLL ON
RF2668
J8 OSC REF
SET1 SET2
C1 1 nF 1 2
48
47
46
45
44
43
42
41
40
39
38
37 36 35 C20 10 nF VCC C26 1 nF C21 2.2 nF R4 36 k C22 220 pF L3 39 nH L2 39 nH C17 10 nF R8* C27 33 pF DO VCC
Band Gap Rel
Bias Supply /R Lock Detect Charge Pump
50 strip L6*
3 4 /N 5 6 7 8 9 10 11
34 33 32 31 30 29 28 T3 T4-1 R7 200 50 strip J7 R9 L01 3.9 k C16* D1 LD
VCC J2 LO2 50 strip
C5 100 pF
VTUNE DO
5
MODULATORS AND UPCONVERTERS
P3 1 2 3
Quad /2
27 26
VCC C9 1 nF 12 13 14 15 16 17 18 19 20 21 22 23 24
2668401-
25
C13 10 nF Chip Enable R2 47 k J6 ISIG REF R6*
Q1 PNP Digikey MMBT3906DICT-ND
R11*
L4* 22 nH C28* 4 pF C11 1 nF R1 39 k VCC C23 10 nF
50 strip
J4 MOD OUT
50 strip
T2 T4-1
LD R5 510 C25 10 nF
C12 1 nF
LD OUT R10 510 k
C24 10 nF 50 strip
*Denotes not normally populated. C10 10 nF R12*
J5 OSIG
VCC
VGC
Rev B4 010423
5-83
RF2668
Evaluation Board Layout 2.500" X 2.250"
Board Thickness 0.031", Board Material FR-4
Preliminary
5
MODULATORS AND UPCONVERTERS
5-84
Rev B4 010423
Preliminary
RF2668
Evaluation Board Layout - Dual Band Output
5
MODULATORS AND UPCONVERTERS
Rev B4 010423
5-85
RF2668
Preliminary
5
MODULATORS AND UPCONVERTERS
5-86
Rev B4 010423

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